Conventional integrated circuit fabrication typically requires the deposition of multiple layers of material within substrate features. For example, as illustratively shown in FIG. 4A, a seed layer 410 may be deposited atop a barrier layer 408 formed on a substrate 400 having one or more features (one shown) 412 formed therein. Conventional theory dictates that an ideal seed layer 410 has a uniform thickness along the sidewalls 414 and bottom 416 of the feature 412, for example, as shown in FIG. 4A. In practice, however, the inventors have observed that conventional seed layer deposition processes do not produce such an ideal geometry and instead typically produce a seed layer 410 having a greater thickness on the sidewalls 414 proximate the opening 411 of the feature 412 as compared to the thickness on the sidewalls 414 proximate the bottom 416 of the feature 412, as depicted in FIG. 4B. Unfortunately, by producing a seed layer 410 having such a geometry, a buildup of seed layer 410 material may occur on the corners 418 of the feature 412, resulting in of the opening 411 of the feature 412 being partially or fully closed, preventing material from filling the feature 412 during subsequent processing.
Accordingly, the inventors have provided improved methods for forming layers on substrates having one or more features formed therein.